Tethered Forth system for FPGA applications

FPGA chips are widely used to build systems with complex functionalities.
Control and testing of such systems often requires complex procedures, which in turn relay on availabity of a CPU.
The CPU built into the FPGA has optimal access to other blocks implemented in the chip, but in typical low cost FPGA the only option is to use the "soft core CPU", which is synthesized together with other components of the IP core and increases the overall memory and logic cells consumption.
In this situation the Forth based CPU is an interesting option, due to low consumption of both - memory and logic resources.
In this paper we present the Forth system well suited for FPGA application.
Its resource requirements are minimized due to the tethered architecture, which at the same time allows us to preserve possibility of interactive operation and defining of new Forth words.
The PC part of the system is implemented in Python, which assures portability to different operating systems.
The FPGA part is implemented in VHDL and is open source.
The connection between the PC and FPGA may be established and disconnected multiple times without disturbing
the state of the FPGA based system. After each reconnection, the compiled Forth words definitions, stored in the FPGA internal memory are verified, to ensure, that they are compatible with the Forth vocabulary stored in the PC part of the system.
The presented system has been verified in the hardware, and may be used as a tool for debugging, diagnosing and implementing of control algorithms for FPGA based systems.