Application of Forth CPU for control and debugging of FPGA-implemented systems

Initialization, control and debugging of FPGA-based systems may be significantly simplified by the availability of a local CPU capable of executing simple programs. In most cases, those programs must be compiled on the host computer and transferred in the binary form to the CPU. The described solution uses the Forth-oriented CPU implemented in HDL. That allows the user to work interactively with the system via a simple UART or JTAG interface and create even complex procedures (Forth words) without a need for an additional compiler.
The Forth words developed in interactive mode may be added to the initial Forth dictionary, which is embedded in the FPGA configuration bitstream. It is also possible to define the particular Forth word as an initialization word, executed automatically after configuration of the FPGA.
The whole presented solution is an efficient tool for control, testing and debugging of the FPGA-based systems.