An FPGA Architecture for MPEG-TS Demultiplexer

This paper presents a novel architecture of MPEG-TS demultiplexer, implemented with FPGA. The main objective of the design was the ability to separate selected elementary streams in real time, while ensuring minimal resource consumption. This was achieved by the decomposition of demultiplexer into a number of independent modules, which process data in parallel. Such flexible structure also enables adaptation to the specific needs and significantly simplifies potential expansion, what is important due to a wide range of applications of the standard. The demultiplexer was equipped with configuration interface, realised as a set of registers. Transport stream and configuration data is supplied to the FPGA by a microcontroller through an External Peripheral Interface (EPI). The data is transmitted to the microcontroller via Ethernet, using the UDP protocol.