Version control friendly project management system for FPGA designs

In complex FPGA designs, usage of version control system is a necessity.
It is especially important in the case of designs developed by many developers or even by many teams.
The standard development mode, however, offered by most FPGA vendors is the GUI based project mode. It is very convenient for a single developer, who can easily experiment with project settings, browse and modify the sources hierarchy, compile and test the design.
Unfortunately, the project configuration is stored in files which are not suited for use with Version Control System (VCS).
Another important problem in big FPGA designs is reuse of IP cores.
Even though there are standard solutions like IEEE 1685-2014, they suffer from some limitations particularly significant for complex systems (e.g. only simple types are allowed for IP-core ports, it is not possible to use parametrized instances of IP-cores).
Additionally, the overhead associated with packaging of IP-cores is significant and not justified for simple reusable blocks.

This paper presents a system aimed at storing the whole design in a VCS oriented form. The hierarchy of sources is described with textual "extended project (EPRJ) files" which are fully controlled by the user and may also be put in a VCS.
Both complex and IP blocks may be easily added to the project just by including the accompanying EPRJ file.
Both absolute and relative file paths may be used which allows the flexible structure of directories. The sources of locally developed IP blocks may be stored in directories located inside the main source tree, while sources of independently developed blocks, using separate VCS repositories, may be located outside that tree.
The environment allows splitting the design into smaller parts, which are synthesized independently. That reduces the time needed to recompile the whole design if only a few blocks are modified.
The system creates the standard project, which can be used for convenient interactive work with the design. After the interactive session, the user should transfer changes of settings into the system files (also under VCS control). With that approach, it is always possible to recreate any stable version of the project from the VCS.
The system also provides a possibility of automated rebuilding of the design from the VCS stored files. That is especially useful for "build servers" used in serious projects. The development of the system was inspired by the needs of firmware development for the CBM experiment.

The system has been developed mainly for Xilinx Vivado tools, but adaptation for Altera Quartus is planned in the nearest future.
The system is developed as a free and Open Source solution.