Implementation of a PCIe-SerDes-DDR3 communications in a multi FPGA data acquisition system

This paper describes the embedded system used to store and transfer large amounts of data in a multichannel data acquisition system for the GEM detector.
System consists of an embedded Mini ITX mainboard connected through the PCI Express (PCIe) link to a backplane FPGA. The backplane FPGA is connected through the SerDes/GTP links to (up to) 4 carrier boards. Each carrier board is connected to (up to) 4 FMC modules. System allows for a high speed data transfers between the ITX mainboard and the backplane or carrier modules. Due to high performance/reliability requirements, special care is taken for a proper data error correction/packet retransmission scenarios.
There is also need for a proper communications diagnostics and a system addressing abstraction.