Optimized Ethernet transmission of acquired data from FPGA to embedded system

This paper presents a simple system consisting of the FPGA core, network protocol and Linux kernel driver,
aimed on efficient transmission of acquired data from the low resources FPGA equipped with Ethernet PHY to the embedded system, responsible for preprocessing of those data and sending them further via standard network links.
The system has been optimized regarding the memory and logic consumption in the FPGA.
Implementation based on the Layer 2 protocol allows to minimize latency of the packet acknowledge, which results
in further reduction of memory requirements at the FPGA side.
The driver code has been optimized to avoid unnecessary copying of data between buffers in memory, allowing the user application to access received data via memory mapped buffer.
The system has been successfuly tested in real hardware.