IPbus TVM in UVVM

Simulation-based functional verification is an important part of a Field-Programmable Gate Array (FPGA) design flow.
It is desirable of test bench to be written quickly, with high abstraction and in understandable way.
The paper describes IPbus Transaction Verification Model (TVM) that has been implemented in the Universal VHDL Verification Methodology (UVVM) test bench infrastructure.
It also presents a simple example how the module should be used.