Encoding of chain outputs in FPGA-based Moore FSMs

T. Gratkowski, A. Barkalov, L. Titarenko, J. Bieganowski

A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on replacement of the state register by a state counter. The specific of the proposed method is that the counter content is incremented for unconditional transitions and conditional transitions. An example of application of proposed method is given.

Author: Jacek Bieganowski
Conference: Title