Reducing Hardware in FPGA-based Mealy FSM

T. Gratkowski, Małgorzata Kołopieńczyk, Larysa Titarenko, Kamil Mielcarek, Alexander Barkalov

This article is devoted to design of Mealy FSM with FPGAs using embedded memory blocks and look-up table elements. There is presented the state-of-the-art. The method is proposed for design of Mealy FSM logic circuit with embedded memory blocks based on encoding of collections of outputs and replacement of inputs. Example of design and research results are given.