Automatic latency equalization in VHDL-implemented complex pipelined systems

FPGA-based high-speed data processing systems often use pipelined architecture to provide required throughput.
If various intermediate operations on data are performed in parallel branches, it is essential that the associated latency (measured in clock periods) are the same. Otherwise, the data arriving at the processing blocks are not properly aligned in time, and incorrect results are produced.
The manual correction of latencies is a tedious and error-prone work. It was a significant problem in the development of the firmware implementing the algorithm for the Overlap Muon Track Finder for the CMS experiment.
This paper presents an automatic method of latency equalization in systems described in VHDL. The method is based on simulation and is portable between different simulation and
synthesis tools. The method does not increase the complexity of the synthesized design comparing to the
solution based on manual latency adjustment. The example implementation of the proposed methodology
together with a simple design demonstrating its use is available as an open source project under BSD license.

Author: Wojciech ZaboŇāotny
Conference: Title