Test systems of the STS/MUCH-XYTER2 ASIC - from wafer-level to in-system verification.

K. KasiƄski, W. Zubrzycka

STS/MUCH-XYTER2 ASIC is a full-size prototype chip for Silicon Tracking System and Muon Chamber detector layers in the new fixed-target experiment Compressed Baryonic Matter at FAIR-center, Darmstadt, Germany. The final system will comprise more than 15000 ASICs assembled into detector stations.
The complicated, time-consuming, multi-step assembly process and tight quality assurance regulations require that only good dies are used and intermediate testing is necessary for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. After assembly is finished and two, 8-chip modules are connected to the 1024-channel double-sided sensor, a final verification is also required. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). The architectures of each chip verification system, show the aims of the tests at each level together with the test
plan, methodology and test coverage are presented.

Author: Weronika Zubrzycka
Conference: Title