Internal monitoring of GBTx emulator using IPbus for CBM experiment

The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at GSI. This experiment will examine heavy-ion collisions in fixed target geometry and will be able to measure hadrons, electrons and muons. A highly time synchronized; fault tolerant self-triggered electronics is required for CBM experiments data acquisition which can support high data rate (up to several TB/s). As a part of the implementation of data acquisition system of Muon Chamber (MUCH) which is one of the important detector in CBM experiment, we have implemented an FPGA based Gigabit Transceiver (GBTx) emulator. Read out chain for MUCH consists of MUCH-XYTER(Front end electronics) which will be directly connected to detector, GBTx emulator, Data Processing Board (DPB) and First level event selector board (FLIB) with backend software interface. GBTx is a radiation hardened ASIC that can be used to implement multipurpose high speed bidirectional optical links for high-energy physics (HEP) experiments and is developed by CERN. Internal architecture of GBTx emulator can be classified into three parts. Front end LVDS (Low Voltage Differential Signalling) line used to connect with MUCH-XYTER, back end 4.8 Gbps optical link and some internal registers. Transmitter of GBTx consists of scrambler (used for line coding and clock data recovery), Reed Solomon (RS) encoder, interleaver (alleviate the effect of burst error) and frame to ward converter block. Similarly in the receiver side there is Descrambler, RS decoder, deinterleaver, word to frame converter block and one pattern search block which is used for frame synchronization. To mitigate the effect of single event upset (SEU) Reed Solomon encoding (15,11) is used. There are eight parallel blocks of RS encoder which can correct eight errors simultaneously. There are three types of frame format that can be used during communication through optical fibre. They are Wide bus mode, 8b/10b mode and GBT mode. Widths of all three frames are 120 bit. In the CBM experiment, wide bus mode will be used during the uplink (from XYTER to the backend) and GBT frame will be used during the downlink (from backend to XYTER). In the GBT frame data field of width 80 bit, 32 bit width forward error correction field, 4 bit header and 4 bit for slow control field. Wide bus mode contains 112 bit data, 4 bit header and 4 bit for slow control. After receiving in the receiver side through optical fibre, data is sent to the computer for testing purpose using scatter gather direct memory access (SGDMA) and Peripheral Component Interconnect Express (PCIe). But in final setup this PCIe interface will be replaced by ten gigabit ethernet to connect with FLIB board. The slow control field in the frame is used for internal and external control and for that purpose GBT-SCA (GBT slow control adaptor) will be used with GBTx ASIC. But in GBTx emulator, IP bus is used with along with ethernet to monitor the internal registers and control it. In IP bus implementation user datagram protocol (UDP) stack is used in transport layer so that we can control the GBTx remotely. To Control GBTx through IPBus, a python based script is written.