The prototype readout chain for CBM using the AFCK board and its software components

The Compressed Baryonic Matter (CBM) experiment will be installed at the future FAIR facility in Darmstadt, Germany. In order to reach the high rate of heavy ion interactions required by its physics goals, it will use a readout system with the following properties:
- continuous readout (data driven)
- time based reconstruction
- online reconstruction, event detection, event building and event selection.
The online event processing will be performed in a computing farm called First Level Event Selector (FLES). Three stages of common hardware will be used for most CBM sub-detectors between their Front End Electronics (FEE) and the FLES:
- readout boards (ROB) with the CERN GBT data transport components (GBTx, VTRx, SCA)
- an FPGA board called Data Processing Board (DPB)
- a PCIe FPGA board hosted in the FLES input nodes, called FLES Input Board (FLIB).
This contribution will present some of the setups to be used for testing the readout chain as components become available, the functional blocks they require in the DPB layer and the corresponding control and acquisition software elements.
All along, the case of the readout chain for the Silicon Tracking System (STS) sub-detector will be used as example. This specific readout chain is built around the STS-XYTER 2 ASIC.