Improvement of FPGA control via high speed, but high latency interfaces

Most modern interfaces, used in computer interfaces to control extension boards or external hardware, offer high throughput, but also relatively high latency.
This fact significantly impairs efficiency of those communication or control algorithms, in which tight handshake is required, and communication consists of sequence of write and read operations, where read result must be checked before the next write command is issued.
The typical solution involves implementation of intelligent controller in the controlled hardware, which accepts high level commands, and locally performs all necessary handshake operations. Unfortunately this approach requires implementation of relatively complex and highly specialized controller.
This paper presents a highly simplified versatile controller, implementable in FPGA, which may improve efficiency of certain, relatively wide class of control algorithms.
The controller accepts a set of simple commands describing the write operations and simple tests associated with read operations.
In case of correct operation of the controlled hardware, the controller only notifies the host about successful completion.
In case if certain handshake test fails, the host is notified about the problem (position of the failed read command, expected data and received data), and the controller may be used in the slower standard mode, allowing the host to invetigate and cure the problem.